HBM-High Bandwidth Memory


HBM was proposed as an industry standard by AMD and Hynix in 2010 and was adopted by JEDEC in 2013.HBM is targeted for high performance graphics accelerator( Nvidia’s pascal based GPUs and AMD’s fiji) and network devices.

HBM,a new type of CPU/GPU memory chip with low power consumption which has ultra wide memory lanes and a revolutionary new stacked configuration.Its vertical stacking and fast information transfer open the door for performance in innovative forms factors.It uses vertically stacked memory chips interconnected by microscopic wires called ” through silicon vias ” or “TSVs”.



In above image,we can see that the HBM Dram die stacks memory chips like floors in skyscraper.Those towers like structure connected to the CPU or GPU through fast interconnect called “interposer”.4 DRAM dies with two channels each which is 8 channels, a total of 1024 bit of bus width.

On package substrate their resides interposer. HBM stacks close to the interposer but physically do not integrate with CPU or GPU.


In GDDR5(current type of graphics memory) memory configuration,alongside the package substrate the memory modules are fixed.

Three problems are faced by the Industry due to GDDR5 memory configuration.

  • GDDR5 can’t keep up with GPU performance growth

                     GDDR5 rising power consumption may stalled the growth of graphics performance.It may reduce the market value of graphic cards in coming years.

  • GDDR5 limits form factors

                     A large number of GDDR5 chips required to reach high bandwidth ,large voltage circuitry is required.It will result in increase in size of graphic cards for desktop and laptops for high end and mid rage graphic cards.

  • On-chip Integration are not ideal for everything

                     Technologies like NAND,DRAM would get benefit from on-chip integration.Everything on the silicon die will result in technological incompatible,but we have to follow moore’s law and will continue with limitations.

Hence the requirement for new kind of memory.


HBM                                               HBM


 HBM                                             Per package                            GDDR5

1024 bit                                          Bus Width                               32 bit

upto 500 MHz(1 Gbps)                Clock Speed                           upto 1750 MHz(7 Gbps)

> 100GB/s per stack                    Bandwidth                              upto 28GB/s per chip

1.3 V                                                  Voltage                                    1.5 V

HBM will use >35 GB/s of bandwidth per watt whereas GDDR5 uses 10.66 GB/s bandwidth per watt.HBM will use 94% less surface area than GDDR5 module.1GB of GDDR5 fits in 28 x 24(in mm) but,1GB of HBM will require 5 x 7 (in mm)


Size comparison between 1GB DDR5 and 1GB HBM


A shot of Fiji GPU was shown at Computex 2015 where you can see how HBM are stacked around the GPU die.To know more about this GPU,stay tuned at here on 16th june 2015


What I came to know?

                   AMD is really striving hard to complete their goal ” 25x energy efficiency by 2020″.This HBM technology talks about the reducing power consumption in future graphic products and accelerated processors,but not by comprising performance.It will outcast both DDR3 and GDDR5 by consuming less power and providing more bandwidth.It can be the next generation memory for all the processors,Graphic processors and Accelerated processors.This will be applicable in Graphics card, HPC and Workstation.small form factors and ultra form factors will have benefit from this kind of memory modules design.This technology standard will also increase the bandwidth.Moore’s law will also continue with some cost challenges.Hence this technology will bring new revolution to the semiconductor industries.

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